Key Points:
- Huawei Technologies introduced the Tau (τ) Scaling Law to bypass U.S. equipment sanctions and continue advancing chip density.
- The company plans to design high-end chips with a transistor density equivalent to a 1.4-nanometer process by 2031.
- The new model replaces traditional geometric miniaturization of transistors with a paradigm shift focusing on time-scaling and LogicFolding.
- Huawei will debut this innovative architecture in its upcoming flagship Kirin mobile processors scheduled to launch in Fall 2026.
Chinese technology giant Huawei Technologies has unveiled a radical new semiconductor design philosophy that could enable it to match the world’s most advanced chips. On Monday, May 25, 2026, He Tingbo, chair of the Huawei Scientist Committee and president of HiSilicon, presented the “Tau (τ) Scaling Law” at a major industry conference in Shanghai. This groundbreaking theoretical model seeks to bypass strict U.S. export controls by showing a new path forward for semiconductor evolution, even without access to the world’s most advanced chipmaking machinery.
The most eye-catching aspect of the announcement is Huawei’s timeline for absolute frontier chip design. Using this new scaling law, the Shenzhen-based company expects to design high-end chips by 2031 with a transistor density equivalent to a 1.4-nanometer (nm) process. This target is highly significant because 1.4 nm-class technology represents the absolute global frontier for semiconductor fabrication, which the industry leader, Taiwan Semiconductor Manufacturing Co. (TSMC), aims to mass-produce in its own state-of-the-art facilities around 2028.
For years, the U.S. government has applied strict sanctions to prevent Chinese firms from obtaining advanced lithography tools. Specifically, Washington has successfully blocked China from purchasing Extreme Ultraviolet (EUV) lithography systems from Dutch manufacturer ASML. These multi-million-dollar machines are essential for traditional “geometric scaling”—the process of physically shrinking transistors to squeeze more onto a single slice of silicon. Without EUV systems, Chinese chipmakers have struggled to advance beyond the older 7-nanometer and 5-nanometer nodes.
To break through this physical and political bottleneck, Huawei’s new scaling law proposes a complete paradigm shift. Instead of focusing solely on the traditional geometric miniaturization of transistors, the Tau Scaling Law prioritizes “time scaling” to shorten the critical signal propagation delay. Named “Her’s Law” by He Tingbo’s scientific peers, this model optimizes the fundamental physics of the silicon wafer. It concentrates on reducing the electrical resistance and parasitic capacitance of transistors to speed up data transmission across the chip.
At the heart of this time-scaling approach is a newly developed circuit-level technology called “LogicFolding” architecture. LogicFolding breaks down the physical boundaries of traditional, rigid circuit layouts. By shortening the critical-path wiring, this design minimizes the resistive and capacitive loads in signal propagation. Ultimately, LogicFolding boosts both transistor density and overall circuit performance without requiring the lithography machine to print physically smaller transistors, effectively resolving a massive manufacturing bottleneck.
Although the announcement represents a major theoretical milestone, the technology is already highly practical. During her keynote speech at the IEEE International Symposium on Circuits and Systems (ISCAS), He Tingbo revealed that Huawei has quietly utilized the Tau Scaling Law to design and mass-produce 381 different chips over the past six years. The company plans to deploy the highly anticipated LogicFolding architecture in a consumer-facing product for the first time this autumn, integrating the design into its flagship Kirin mobile processors, which are scheduled to launch in Fall 2026.
Beyond smartphone processors, Huawei is also applying the Tau Scaling Law to its multi-billion-dollar artificial intelligence (AI) and server business. The company is using this system-level architecture to redefine interconnect protocols with its proprietary “UnifiedBus”. By establishing unified memory addressing and native memory semantics, UnifiedBus significantly reduces system communication latency for SuperPoDs—massive clusters of AI servers that compete directly with Nvidia’s flagship AI hardware.
This domestic innovation comes as global analysts estimate that China now invests upwards of $12 billion annually into establishing a fully self-reliant semiconductor ecosystem. With Nvidia’s CEO, Jensen Huang, recently conceding that U.S. export controls have effectively pushed Chinese buyers toward domestic alternatives, Huawei has expanded its market share by over 15% in China’s AI data center sector. By doubling its production of top-end Ascend AI chips, the company is positioning itself as China’s primary supplier of high-performance computing power.
While Western skeptics note that Huawei has not yet released independent performance benchmarks for its 1.4nm-equivalent design, the announcement has sent ripples through the global tech sector. By shifting the chipmaking focus from geometric shrinking to physical time-scaling, Huawei is showing that national-security restrictions can sometimes accelerate, rather than halt, domestic engineering breakthroughs. The coming years will prove whether this time-scaling law can truly dismantle TSMC’s long-standing semiconductor sovereignty.
