Key Points:
- Samsung Electronics joined an ASML-led industry consortium to transition from 6-inch to next-generation 12-inch photomasks.
- The company plans to introduce High NA EUV lithography into high-volume DRAM memory manufacturing by 2028.
- Transitioning to 12-inch masks removes stitching constraints, boosts fab productivity, and cuts chipmaking costs for AI silicon.
- High NA EUV raises optical numerical aperture from 0.33 to 0.55 to print finer circuits for next-generation memory and logic chips.
South Korean semiconductor leader Samsung Electronics has joined an international technology consortium led by Dutch lithography equipment maker ASML to pioneer next-generation 12-inch photomask technology. The strategic collaboration aims to replace the legacy 6-inch photomask format that the global semiconductor industry has used for decades. The initiative will boost wafer fab productivity, remove intricate manufacturing bottlenecks, and significantly lower production expenses as artificial intelligence workloads drive record demand for cutting-edge microchips.
Alongside the photomask partnership, Samsung announced plans to deploy ASML’s High Numerical Aperture (High NA) extreme ultraviolet (EUV) lithography systems into commercial high-volume manufacturing of dynamic random-access memory (DRAM) by 2028. The deployment will mark the first time an automaker or memory producer integrates High NA EUV equipment into mass memory chip fabrication. The milestone extends Samsung’s DRAM scaling roadmap, allowing engineers to print finer electrical circuits and simplify complex multi-exposure manufacturing steps.
Photomasks function as high-precision master templates etched with microscopic circuit patterns that lithography machines project onto silicon wafers using laser light. For over forty years, the global semiconductor industry has relied exclusively on a standard 6-inch by 6-inch quartz mask format. However, as chip designs grow larger and transistors shrink to atomic scales, traditional 6-inch masks face severe physical limits, forcing chipmakers to split large processor patterns into multiple smaller exposures.
This physical constraint became acute with the advent of High NA EUV lithography. High NA systems increase the optical numerical aperture from 0.33 to 0.55, allowing lenses to capture and focus light with superior resolution. However, the higher magnification halves the traditional reticle exposure field, forcing chipmakers to use an engineering workaround known as mask stitching. In mask stitching, machines expose half of a microchip circuit pattern at a time and stitch the edges together on the wafer, which slows down fab throughput and introduces alignment risks.
Transitioning to larger 12-inch photomasks completely eliminates the stitching bottleneck by quadrupling the surface area available on a single quartz plate. The expanded format allows lithography scanners to project full-sized, ultra-dense microchip designs in a single optical pass. By reducing the number of individual wafer exposures required per layer, 12-inch masks will significantly increase cleanroom scanner productivity, improve silicon die yields, and lower the unit cost of advanced memory and logic chips.
Samsung brings unique industrial advantages to the ASML-led consortium as the only global semiconductor company that operates both market-leading memory fabrication lines and an advanced commercial logic foundry. The tech giant will collaborate closely with mask suppliers, quartz substrate makers, and inspection tool builders to establish unified industry standards, develop automated mask-handling robots, and test specialized chemical pellicles designed to protect 12-inch masks from microscopic airborne contaminants.
The planned integration of High NA EUV into DRAM manufacturing builds upon Samsung’s established leadership in memory scaling. Samsung became the first chipmaker in the world to introduce standard EUV lithography to commercial DRAM production in 2020. Deploying 0.55 NA systems by 2028 will enable the company to produce sub-10-nanometer DRAM generations, providing the ultra-dense memory architectures required for next-generation High Bandwidth Memory (HBM4 and HBM4E) modules that power artificial intelligence supercomputers.
The initiative arrives as global semiconductor manufacturers race to secure technological dominance in the generative artificial intelligence era. As artificial intelligence models expand to trillions of parameters, cloud hyperscalers require memory chips and custom processors with higher data bandwidth, lower power consumption, and tighter transistor density. Samsung Electronics Chief Executive Officer Jun Young-hyun noted that technological breakthroughs across the entire semiconductor supply chain are essential to power the next wave of artificial intelligence hardware.
The large-format photomask consortium marks a broader push across the global semiconductor ecosystem to support ASML’s advanced tool roadmap. Major international chipmakers, including Taiwan Semiconductor Manufacturing Company (TSMC) and Intel, are participating in collaborative industry initiatives to align cleanroom infrastructure with 12-inch mask standards. By uniting the world’s top chipmakers behind a single standard, equipment makers can accelerate commercial availability while lowering development costs for all participants.
As engineering teams in South Korea and the Netherlands begin testing prototype mask-handling systems, Samsung’s dual commitment to 12-inch photomasks and High NA DRAM fabrication solidifies its position at the forefront of semiconductor innovation. By modernizing decades-old lithography standards and shrinking memory circuitry, Samsung and ASML are establishing the manufacturing foundation that will power advanced computing for the next generation.
