Mizuho Securities Asia aggressively raised its monthly advanced packaging capacity forecasts for Taiwan Semiconductor Manufacturing Company (TSMC). The upward revision reflects a surging global demand for artificial intelligence infrastructure and next-generation server central processing units (CPUs). This development signals that TSMC’s massive manufacturing footprint must expand significantly faster than previously modeled to satisfy accelerating orders from global chip designers and hyperscale cloud providers.
According to the updated semiconductor supply model, Mizuho increased its forecast for TSMC’s monthly Chip-on-Wafer-on-Substrate (CoWoS) packaging capacity to 140,000 units by the end of 2026, up from its previous estimate of 120,000. For 2027, the firm raised its monthly projection to a range of 190,000 to 200,000 units, up from its prior forecast of 170,000 to 180,000. This rapid capacity expansion is a direct response to a sharply upgraded demand outlook for high-performance server processors, including Nvidia’s newly launched Vera CPU, advanced server CPUs from AMD and Intel, and custom application-specific integrated circuits (ASICs) designed by cloud service providers like Google, Amazon, Microsoft, and Meta.
The Core Numbers Behind Mizuho’s Aggressive Capacity Revisions
The upward revision to TSMC’s packaging capacity runs in parallel with a major upgrade to Mizuho’s individual customer demand forecasts. The updated data reveals that the world’s largest technology companies are competing aggressively to book TSMC’s highly limited manufacturing slots, driving an unprecedented volume of orders for the next two years.
For Nvidia, Mizuho now projects a total of 630,000 CoWoS units at TSMC in 2026, a figure that is expected to climb to an extraordinary 1,005,000 units in 2027. This massive 57% year-over-year surge in packaging demand is primarily driven by accelerating orders for Nvidia’s Vera CPU throughout 2026 and 2027, alongside a rapid ramp-up in production for its next-generation Rubin GPU architecture.
Other major players in the custom chip and ASIC markets are also seeing significant adjustments to their capacity allocations. Mizuho nearly doubled its 2027 CoWoS demand estimate for MediaTek, raising it to 180,000 units from a previous projection of 93,000, a massive increase driven by Google’s surging demand for its custom Tensor Processing Units (TPUs). Meanwhile, the firm trimmed its 2027 CoWoS projection for Broadcom slightly to 425,000 units from 450,000. Despite this minor downward adjustment, Broadcom remains TSMC’s second-largest advanced packaging customer, largely due to its role in manufacturing Meta’s custom AI chips and Google’s high-volume hardware networks.
Resolving the Advanced Packaging Bottleneck
In the current semiconductor market, the primary constraint on artificial intelligence hardware is no longer raw silicon wafer fabrication. Instead, advanced packaging has emerged as the ultimate bottleneck gating the delivery of high-end processors. Modern AI chips, such as Nvidia’s Blackwell or AMD’s Instinct accelerators, are too large and complex to be manufactured on a single piece of silicon. Instead, they rely on a chiplet architecture, where multiple smaller processing cores and high-speed High-Bandwidth Memory (HBM) modules are placed side-by-side and connected on a high-density substrate.
TSMC’s proprietary CoWoS technology is the industry standard for this advanced 2.5-dimensional integration. Because the demand for these integrated packages has far outpaced available manufacturing capacity, the industry has faced a prolonged supply shortage. In mid-2026, the global CoWoS supply-demand gap hovers around 20%, forcing hardware buyers to wait months for deliveries. However, TSMC’s aggressive capital investments—including the construction of its massive new AP8 advanced packaging facility in Tainan—are beginning to narrow this gap. Industry analysts expect the CoWoS supply deficit to contract to approximately 10% by the end of 2026, with further stabilization expected in 2027 as new manufacturing lines reach full operational capacity.
The Extreme Concentration Risk in the Advanced Packaging Supply Chain
While the planned capacity expansion offers some relief to the broader technology sector, the advanced packaging supply chain remains characterized by extreme customer concentration. The world’s largest chip designers have secured the vast majority of TSMC’s available CoWoS capacity, leaving very little room for smaller competitors and emerging startups.
This concentration risk is particularly visible when looking at individual client bookings:
- Nvidia alone consumes more than 60% of TSMC’s total CoWoS output, having pre-booked more than half of the foundry’s planned 2026–2027 capacity expansion.
- The top three advanced packaging customers—Nvidia, Broadcom, and AMD—collectively control more than 85% of TSMC’s total CoWoS capacity.
- Major hyperscalers and custom ASIC designers, such as Google, Meta, and Amazon, account for the majority of the remaining 15% of capacity.
This extreme consolidation means that smaller AI chip design startups are effectively locked out of TSMC’s premier packaging lines. Unable to secure advanced packaging, many smaller firms must rely on legacy packaging technologies or wait for potential order spillovers to secondary packaging providers, slowing down their development cycles and limiting their ability to challenge the market leaders.
The Exponential Rise of TSMC’s AI Revenue Stream
The massive demand for advanced packaging is transforming TSMC’s corporate financial profile, turning what was once a specialized secondary service into a core profit engine. According to institutional research from Morgan Stanley, TSMC’s AI-related revenue is projected to hit an extraordinary $8.63 billion in 2027, representing a staggering 218% year-on-year increase from the $2.71 billion expected in 2026.
This multi-billion-dollar revenue stream demonstrates that advanced packaging has achieved equal strategic importance to traditional wafer fabrication. A breakdown of the projected $8.63 billion in 2027 AI revenue reveals the diverse nature of this business: $2.8 billion will come from GPU manufacturing, $1.8 billion from custom AI ASICs, $4.0 billion directly from CoWoS advanced packaging services, and $300 million from AI server CPUs. By 2028, this AI-related revenue is expected to climb further to $10.66 billion. Because TSMC commands gross profit margins exceeding 50% on its high-end packaging services, this segment will continue to drive exceptional earnings growth for the Taiwanese giant.
Next-Generation CoPoS Technology: Moving from Round to Square
To address the physical and economic limits of current packaging methods, TSMC is accelerating the development of its next-generation advanced packaging platform: CoPoS (Chip-on-Panel-on-Substrate). This technology represents a fundamental shift in how chips are assembled, transitioning production from traditional round 12-inch silicon wafers to large, square panels measuring 310mm by 310mm.
The economic logic behind this round-to-square transition is straightforward. As modern AI processors grow larger and incorporate more chiplets, they consume an increasing amount of reticle space. When printing these massive, rectangular chip assemblies on a circular silicon wafer, a significant amount of expensive interposer material along the curved outer edges of the wafer goes to waste. Square panels eliminate this edge waste almost entirely, allowing manufacturers to squeeze more chips onto a single substrate and reduce average manufacturing costs by up to 20%.
TSMC has already established an active R&D and pilot production line for CoPoS at its VisEra subsidiary’s Longtan plant. While the company has imposed strict non-disclosure and exclusive-supply clauses on its equipment and material providers to protect its intellectual property, industry sources indicate that pilot production is targeted for mid-2027. Full-scale mass production is expected to begin between 2028 and 2029, with Nvidia’s upcoming Feynman platform slated to be the first commercial customer to adopt the panel-level technology.
Intel’s EMIB Alternative and the Battle for Packaging Dominance
While TSMC currently commands approximately 70% of the global 2.5D advanced packaging market, it faces a growing competitive threat from Intel Corporation. Intel has quietly built a meaningful technological and cost advantage through its proprietary Embedded Multi-Die Interconnect Bridge (EMIB) packaging technology, which is emerging as a lower-cost alternative to TSMC’s CoWoS-L.
The primary difference between the two competing technologies lies in their structural design:
- TSMC CoWoS-L: Relies on a full, continuous silicon interposer—essentially a massive, expensive slab of silicon that sits underneath the entire chiplet assembly, raising packaging costs significantly.
- Intel EMIB: Utilizes localized, microscopic silicon bridges embedded directly into the substrate to connect neighboring chiplets, sidestepping the need for a full silicon interposer and cutting packaging costs by up to 30%.
- Market Traction: Intel’s cost-effective EMIB technology has already attracted several major enterprise clients, including Amazon, Cisco, SpaceX, and Tesla. Wall Street analysts estimate that Intel’s advanced packaging sales will double by late 2026, giving the U.S. chipmaker a 13.7% share of global 2.5D packaging capacity.
While TSMC’s CoWoS lines remain the gold standard for high-performance GPU training clusters, Intel’s EMIB offers a highly attractive, cost-effective alternative for companies designing custom inference chips and ASICs. This competitive pressure will force both manufacturers to continuously improve their production yields and lower their average selling prices, accelerating the democratization of advanced packaging technology across the global tech sector.
The Broader Impacts of the Server CPU Surge
The rapid expansion of advanced packaging capacity is closely tied to a significant shift in how tech companies design their AI data centers. During the initial phase of the AI boom, capital expenditures focused almost entirely on purchasing GPUs to train large language models. However, as these models move into the deployment and inference phases, the demand for high-performance server CPUs has surged.
Modern AI workloads require high-performance CPUs to manage data preprocessing, coordinate network traffic, handle system virtualization, and orchestrate complex, multi-step workflows. As a result, a single modern AI server rack now requires a much higher ratio of high-performance CPUs alongside the standard GPU clusters. The launch of advanced, integrated processors like Nvidia’s Vera CPU—which combines a high-performance Grace CPU core with next-generation GPU architecture on a single package—has intensified the demand for advanced packaging, as these unified systems require complex, high-density interconnections that only technologies like CoWoS can provide.
Conclusion
Mizuho Securities Asia’s decision to lift its monthly CoWoS capacity forecasts for TSMC highlights the immense, sustained momentum of the global AI infrastructure buildout. By raising its 2027 monthly packaging forecast to a range of 190,000 to 200,000 units, the firm recognizes that advanced packaging remains the primary gateway for next-generation technology. Driven by a surging demand for AI-focused server CPUs and custom ASICs from the world’s largest cloud providers, TSMC’s advanced packaging segment has evolved into a lucrative, multi-billion-dollar business that will generate exceptional revenue growth for the Taiwanese foundry.
While the current supply-demand gap of 20% continues to create near-term bottlenecks, the rapid expansion of TSMC’s domestic packaging facilities and strategic outsourcing to OSAT partners will help stabilize the market over the next twelve months. At the same time, the transition to next-generation panel-level CoPoS technology and the competitive threat from Intel’s EMIB show that the advanced packaging race is entering a highly dynamic, innovative phase. As technology giants continue to scale up their computing power, TSMC’s ability to mass-produce these complex, integrated silicon systems will remain the essential foundation driving the global digital revolution.
